technical data 1 8-bit shift register high-voltage silicon-gate cmos the iw4021b is an edge-triggered 8-bit shift register (parallel- to-serial converter) with a synchronous serial data input (d s ), a clock input (cp), an asynchronous active high parallel load input (pl), eight asynchronous parallel data inputs (p 0 -p 7 ) and buffered parallel outputs from the last three stages (q 5 -q 7 ). information on the parallel data inputs (p0-p7) is asynchronously loaded into the register while the parallel load input (pl) is high, independent of the clock (cp) and serial data (d s ) inputs. data present in the register is stored on the high-to-low transition of the parallel load input (pl). when the parallel load input is low, data on the serial data input (d s ) is shifted into the first register position and all the data in the register is shifted one position to the right on the low-to-high transition of the clock input (cp). ? operating voltage range: 3.0 to 18 v ? maximum input current of 1 a at 18 v over full package- temperature range; 100 na at 18 v and 25 c ? noise margin (over full package temperature range): 1.0 v min @ 5.0 v supply 2.0 v min @ 10.0 v supply 2.5 v min @ 15.0 v supply iw4021b ordering information iw4021bn plastic IW4021BDW soic t a = -55 to 125 c for all packages pin assignment logic diagram pin 16 =v cc pin 8 = gnd function table serial operation: tcpd s pl q 5 t=n+6 q 6 t=n+7 q 7 t=n+8 n000 n+1 1 0 1 0 n+2 0 0 0 1 0 n+3 1 0 1 0 1 x0 q 5 q 6 q 7 parallel operation: cp d s pl p 5 p 6 p 7 q 5 q 6 q 7 x x 1 dddddd x = don?t care d = 1 or 0
iw4021b 2 maximum ratings * symbol parameter value unit v cc dc supply voltage (referenced to gnd) -0.5 to +20 v v in dc input voltage (referenced to gnd) -0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) -0.5 to v cc +0.5 v i in dc input current, per pin 10 ma p d power dissipation in still air, plastic dip+ soic package+ 750 500 mw p d power dissipation per output transistor 100 mw tstg storage temperature -65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip or soic package) 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. +derating - plastic dip: - 10 mw/ c from 65 to 125 c soic package: : - 7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 3.0 18 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types -55 +125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
iw4021b 3 dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limit symbol parameter test conditions v -55 c25 c 125 c unit v ih minimum high-level input voltage v out =0.5 v or v cc - 0.5 v v out =1.0 v or v cc - 1.0 v v out =1.5 v or v cc - 1.5 v 5.0 10 15 3.5 7 11 3.5 7 11 3.5 7 11 v v il maximum low -level input voltage v out =0.5 v or v cc - 0.5 v v out =1.0 v or v cc - 1.0 v v out =1.5 v or v cc - 1.5 v 5.0 10 15 1.5 3 4 1.5 3 4 1.5 3 4 v v oh minimum high-level output voltage v in =gnd or v cc 5.0 10 15 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 v v ol maximum low-level output voltage v in =gnd or v cc 5.0 10 15 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 v i in maximum input leakage current v in = gnd or v cc 18 0.1 0.1 1.0 a i cc maximum quiescent supply current (per package) v in = gnd or v cc 5.0 10 15 20 5.0 10 20 100 5.0 10 20 100 150 300 600 3000 a i ol minimum output low (sink) current v in = gnd or v cc v ol =0.4 v v ol =0.5 v v ol =1.5 v 5.0 10 15 0.64 1.6 4.2 0.51 1.3 3.4 0.36 0.9 2.4 ma i oh minimum output high (source) current v in = gnd or v cc v oh =2.5 v v oh =4.6 v v oh =9.5 v v oh =13.5 v 5.0 5.0 10 15 -2.0 -0.64 -1.6 -4.2 -1.6 -0.51 -1.3 -3.4 -1.15 -0.36 -0.9 -2.4 ma ac electrical characteristics (c l =50pf, r l =200 k ? , input t r =t f =20 ns) v cc guaranteed limit symbol parameter v -55 c25 c 125 c unit f max maximum clock frequency 5.0 10 15 3.0 6.0 8.5 3.0 6.0 8.5 1.5 3.0 4.25 mhz t plh , t phl maximum propagation delay, cp to qn 5.0 10 15 320 160 120 320 160 120 640 320 240 ns t plh , t phl maximum propagation delay, pl to qn 5.0 10 15 320 160 120 320 160 120 640 320 240 ns t tlh , t thl maximum output transition time, any output 5.0 10 15 200 100 80 200 100 80 400 200 160 ns c in maximum input capacitance 5.0 7.5 pf
iw4021b 4 timing requirements (c l =50pf, r l =200 k ? , input t r =t f =20 ns) v cc guaranteed limit symbol parameter v -55 c25 c 125 c unit t w minimum pulse width cp 5.0 10 15 160 80 50 160 80 50 320 160 100 ns t w minimum pulse width pl 5.0 10 15 180 80 50 180 80 50 360 160 100 ns t su minimum setup time, d s tocp 5.0 10 15 120 80 60 120 80 60 240 160 120 ns t su minimum setup time, pn to pl 5.0 10 15 50 30 20 50 30 20 100 60 40 ns t h minimum hold time, d s tocp 5.0 10 15 0 0 0 0 0 0 0 0 0 ns t h minimum hold time, pn to pl 5.0 10 15 0 0 0 0 0 0 0 0 0 ns t rec minimum recovery time pl 5.0 10 15 280 140 100 280 140 100 560 240 200 ns t r , t f maximum input rise or fall time 5.0 10 15 15 15 15 15 15 15 15 15 15 s expanded logic diagram
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